Logic Gate Half Adder

ESP32 DevKit (WROOM-32)·Arduino C++·Updated Jul 27, 2026·by FluxBench TeamIncludes Lab + Schematic + PCB

Digital-logic starter bench: a 1-bit half adder built from two 74HC-style gate modules — an XOR gate computes SUM and an AND gate computes CARRY. The ESP32 walks the inputs through the full truth table, reads the gate outputs back, and verifies them live; each output also drives an LED so you can watch the adder count. The gates are solved from real voltages in the Lab, so pulling a power wire mid-run genuinely breaks the adder and the sketch reports the mismatch. Bundled Lab bench, schematic and routed PCB included.

sketch.ino

// Logic Gate Half Adder — XOR makes SUM, AND makes CARRY
#define PIN_A 25
#define PIN_B 26
#define PIN_SUM 32
#define PIN_CARRY 33

int combo = 0;
int errors = 0;

void setup() {
  Serial.begin(115200);
  pinMode(PIN_A, OUTPUT);
  pinMode(PIN_B, OUTPUT);
  pinMode(PIN_SUM, INPUT);
  pinMode(PIN_CARRY, INPUT);
  Serial.println("Half adder trainer: SUM = A XOR B, CARRY = A AND B");
  Serial.println(" A B | SUM CARRY");
}

void loop() {
  int a = (combo >> 1) & 1;
  int b = combo & 1;
  digitalWrite(PIN_A, a);
  digitalWrite(PIN_B, b);
  delay(60); // let the gates settle
  int sum = digitalRead(PIN_SUM);
  int carry = digitalRead(PIN_CARRY);
  Serial.print(" ");
  Serial.print(a);
  Serial.print(" ");
  Serial.print(b);
  Serial.print(" |  ");
  Serial.print(sum);
  Serial.print("    ");
  Serial.print(carry);
  if (sum == (a ^ b) && carry == (a & b)) {
    Serial.println("   ok");
  } else {
    Serial.println("   MISMATCH");
    errors++;
  }
  combo++;
  if (combo == 4) {
    if (errors == 0) {
      Serial.println("Truth table verified - half adder works!");
    } else {
      Serial.println("Check your wiring - mismatches found.");
    }
    combo = 0;
    errors = 0;
    Serial.println(" A B | SUM CARRY");
  }
  delay(1940);
}

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